The Peripheral component interconnect (PCI) bus is a bus standard developed to enable applications to transfer data between a microprocessor bus, also called a local bus, and peripheral devices. The current PCI standard uses a 32-bit data path, a 33 MHZ clock speed and a maximum data transfer rate of 132 MB/sec. A 64-bit specification exists for future PCI designs, which will double data transfer performance to 264 MB/sec.
Conventional applications employ the PCI bus in a bridged architecture. A PCI bridge architecture uses a de-ccupling bridge to isolate the local bus from the PCI bus. The microprocessor writes data to a target PCI peripheral by first writing the data to the PCI bridge, and the PCI bridge moves the data to the target PCI peripheral (data is obtained from a PCI peripheral in a similar manner, but in the opposite direction). One advantage of the bridged architecture is that it allows the microprocessor to perform its next operation rather than waiting for the transfer to complete, and the buffer in the PCI bridge feeds the data to the target peripheral at the most efficient rate possible.
The use of a PCI bridge in a conventional bridged architecture, however, also entails disadvantages. Most conventional PCI bridges use complex translation methods or schemes such as FIFO buffering, data prefetching, and coherence, which increases system complexity and lead to higher cost applications. Additionally, such schemes increase data latency, making applications more difficult to design and trouble-shoot.
One application employing this conventional bridged architecture in a PCI based system is an asynchronous digital subscriber line (ADSL) router. In a conventional ADSL router, an ADSL bit pump couples to an "off the shelf" segmentation and reassembly (SAR) chip, which in turn is coupled to a PCI bus as a PCI device. The PCI bus provides access to a local bus through a PCI bridge, such that a microprocessor can access the SAR as a target PCI device. Another peripheral device on the PCI bus may be a connectivity device, such as an Ethernet 10/100 interface.
Such conventional routers have disadvantages. The bridged architecture leads to higher application cost and a more difficult application to design and trouble-shoot, as discussed above. Additionally, the "off the shelf" SAR silicon are usually designed to provide access to 155 Mbit/sec ATM networks. Such performance is not necessary for the slower speed ADSL applications, which require transfer rates of about 10 Mbit/sec. Such over-design, once again, leads to higher application cost.